Forum Discussion
Altera_Forum
Honored Contributor
11 years agoHello,
I was also facing same problem and I could solve it by adding "altera_lnsim_ver" library. ( This library is for verilog. And same can be found for VHDL. ) I was simulating Stratix V device in Quartus 13.1. Hope this would be helpful to someone. Cheers, Bhaumik