Simulation Problem about a D filp flop by modelsim ALTERA 10.1d

Why reg and wire have different behaviors in RTL simulation?

module FIFO# (parameter WIDTH = 8, DEPTH = 16)
    (
    input  DataIn,
    input RdReq,
    input WtReq,
    input Clk,
    input Reset,
    output reg  DataOut,
    output reg Full,
    output reg Empty);
    reg  writep;
    reg  readp;
    reg  memory;
    reg  tempwp;
    reg  temprp;
    
    reg almostfull;
    reg almostempty;
    
    reg rdreqbuffer;
    reg rd;
    reg wtreqbuffer;
    reg wtreqbuffer3;
    reg wt;
    
    integer fifo_i;
    
    always@(*) rd = (~rdreqbuffer) & RdReq;
    always@(*) wt = (~wtreqbuffer) & WtReq;
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            rdreqbuffer <= 1;
        else
            rdreqbuffer <= RdReq;
    end
    
    always@(WtReq) wtreqbuffer3 = WtReq;
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            wtreqbuffer <= 1;
        else
            wtreqbuffer <= wtreqbuffer3;
    end
    
    
    always@(writep)
        tempwp = writep + 1'b1;
    
    always@(readp)
        temprp = readp + 1'b1;
    
    always@(tempwp,temprp,writep,readp)
    begin
        almostfull = (tempwp == readp)?1'b1:1'b0;
        almostempty = (temprp == writep)?1'b1:1'b0;
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            for(fifo_i = 0; fifo_i < DEPTH; fifo_i = fifo_i + 1)
            begin
                memory <= 0;
            end
        else if(wt == 1 && Full == 0)
            for(fifo_i = 0; fifo_i < DEPTH; fifo_i = fifo_i + 1)
            begin
                memory <= (writep == fifo_i)?DataIn:memory;
            end
        else
            for(fifo_i = 0; fifo_i < DEPTH; fifo_i = fifo_i + 1)
            begin
                memory <= memory;
            end
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            DataOut <= 0;
        else if(rd == 1 && Empty == 0)
            DataOut <= memory;
        else
            DataOut <= DataOut;
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            writep <= 0;
        else if(wt == 1 && Full == 0)
            writep <= writep + 1'b1;
        else
            writep <= writep;
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            readp <= 0;
        else if(rd == 1 && Empty == 0)
            readp <= readp + 1'b1;
        else
            readp <= readp;
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            Empty <= 1;
        else if((almostempty == 1 && rd == 1 && wt == 0) || (Empty == 1 && wt == 0))
           Empty <= 1;
        else
            Empty <= 0;            
    end
    
    always@(posedge Clk or negedge Reset)
    begin
        if(Reset == 0)
            Full <= 0;
        else if((almostfull == 1 && wt == 1 && rd == 0) || (Full == 1 && rd ==0))
           Full <= 1;
        else
            Full <= 0;            
    end
    function integer widthOf;
        input    integer num;
        if(num == 0) 
            widthOf = 1;
        else 
            for(widthOf = 0; num != 0; widthOf = widthOf + 1) num = num>>1;
    endfunction
endmodule

`timescale 10ps/1ps
module FIFO_tb  ; 
parameter WIDTH  = 8 ;
parameter DEPTH  = 16 ; 
  reg    DataIn   ; 
  wire    DataOut   ; 
  reg    Clk; 
  reg    RdReq   ; 
  wire   Empty   ; 
  wire   Full   ; 
  reg    Reset   ; 
  reg    WtReq   ; 
  FIFO   # ( WIDTH , DEPTH)
   DUT  ( 
       .DataIn (DataIn ) ,
      .DataOut (DataOut ) ,
      .Clk (Clk ) ,
      .RdReq (RdReq ) ,
      .Empty (Empty ) ,
      .Full (Full ) ,
      .Reset (Reset ) ,
      .WtReq (WtReq ) ); 
  initial 
  begin 
  Clk <= 1'b1;
  forever# 10  Clk <= !Clk;
  end
  
  integer i,j;
  
  initial
  begin
 # 80
  for ( i = 1 ; i < 9; i = i + 1) 
  begin
   # 20 DataIn <= i;
  end  
  end
  
  initial
  begin
  WtReq <= 0;  
 # 100 WtReq <= 1;
 # 160  WtReq <= 0; 
  end
  
  initial
  begin
  RdReq <= 0;  
 # 12 //RdReq = 1;
  for ( j = 1 ; j < 18; j = j + 1) 
  begin
   # 20 RdReq <= j%2;
  end 
  end
  
  initial
  begin
  Reset <= 0;
 # 5  Reset <= 1;
  end
endmodule