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No desciption in this thread?
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I just find this problem when I do RTL simulation with upper code. It's easy to find the same problem use the following code.
module test(
input Clock,
input Reset,
input Signal,
output SignalPosEdge
);
//reg signal;
//always@(*) signal = Signal;
reg signalbuffer1;
clkctrl gclk(
.inclk(Clock),
.outclk(gclock)
);
always@(posedge gclock or negedge Reset)
begin
if(Reset == 0)
signalbuffer1 <= 0;
else
signalbuffer1 <= Signal;
// signalbuffer1 <= signal;
end
assign SignalPosEdge = (~signalbuffer1)&Signal;
endmodule
`timescale 1ns/100ps
module test_tb ;
reg Clock ;
wire SignalPosEdge ;
reg Signal ;
reg Reset ;
test
DUT (
.Clock (Clock ) ,
.SignalPosEdge (SignalPosEdge ) ,
.Signal (Signal ) ,
.Reset (Reset ) );
initial
begin
Clock = 1;
forever# 10 Clock = ~Clock;
end
initial
begin
Reset = 0;
# 40 Reset = 1;
end
initial
begin
Signal = 0;
# 40 Signal = 1;
end
endmodule
In the module, test, I want to synchronize Signal's posedge to a cycle of Clock. So I user a D filp-flop to buffer Signal, and use "SignalPosEdge = (~signalbuffer1)&Signal" to get the synchronized pulse. But if using my testbanch, you will only find SignalPosEdge have a risk issue at# 40, being 1 and getting down immediately. While I hope there is one cycle Clock pulse to indicate the posedge of Signal. And if you use the comment sentences in the module, test and the same testbanch, you will find that RTL simulation result is quite different. There is a cycle long pulse in SignalPosEdge.
Thank you for your reading. Please forgive my poor English.
Honored Contributor
