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Altera_Forum
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17 years ago

simulation performance (VCS) and altsyncram

Hello

I noticed some interesting things looking at VCS simulation profiler reports:

- the simulator spends about 40% of CPU time in altera_mf, specifically - in altsyncram combinational assignments.

- after upgrading altera_mf.v from 2005 version to the latest one, simulation time of the same design (for CycloneII) degraded by more than 100%!

- with latest altera_mf.v, about 45% of CPU time is spent on ALTERA_DEVICE_FAMILIES block.

Could anyone confirm these observations, also maybe on other simulation tools?

I see that a lot of effort is spent in parametrized constructs, as if parameters are treated like variables by the simulator, so it could be a VCS problem.

I'd appreciate any help with this issue.

Thanks

Michael

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    I don't have direct experience, but the one I've always heard about is the PLL models. Basically they run internally at high speeds, and a ton of cycles are spent just modeling these certain characteristics. I've heard of many people replacing them with a simpler model(just a behavioral clock, for example). They don't get things like the lock signal going away, but since they're simulating with a perfect clock to begin with, they usually don't care. Since that model is probably in the altera_mf library(I think), it may be what you're experiencing. I haven't heard anything about the rams, or at least anyone find a better way to do them.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I've got a PLL in this design, but it doesn't even appear on the list of the top stars in profiler report.

    From the looks of it, I think that VCS treats muxes with parameter as selector like normal combinational muxes, and altera models have plenty of those. I have no other explanation, but the numbers speak for themselves and this performance degradation is intolerable.

    Here is a quote (altera_mf from Quartus 8.1):

    ================================================================================

    MODULE VIEW

    ================================================================================

    (index) Module %%totaltime No of Instances Definition

    --------------------------------------------------------------------------------

    (1) altera_device_families 48.21 90 /home/michaelv/tests/michaelv_VLSI_dev/VLSI_common/models/altera/cyclone/rtl/altera_mf.v:1354.

    (2) altsyncram 16.57 89 /home/michaelv/tests/michaelv_VLSI_dev/VLSI_common/models/altera/cyclone/rtl/altera_mf.v:42597.