simulation performance (VCS) and altsyncram

I don't have direct experience, but the one I've always heard about is the PLL models. Basically they run internally at high speeds, and a ton of cycles are spent just modeling these certain characteristics. I've heard of many people replacing them with a simpler model(just a behavioral clock, for example). They don't get things like the lock signal going away, but since they're simulating with a perfect clock to begin with, they usually don't care. Since that model is probably in the altera_mf library(I think), it may be what you're experiencing. I haven't heard anything about the rams, or at least anyone find a better way to do them.