Honored Contributor
Honored ContributorI've got a PLL in this design, but it doesn't even appear on the list of the top stars in profiler report.
From the looks of it, I think that VCS treats muxes with parameter as selector like normal combinational muxes, and altera models have plenty of those. I have no other explanation, but the numbers speak for themselves and this performance degradation is intolerable. Here is a quote (altera_mf from Quartus 8.1): ================================================================================ MODULE VIEW ================================================================================ (index) Module %%totaltime No of Instances Definition -------------------------------------------------------------------------------- (1) altera_device_families 48.21 90 /home/michaelv/tests/michaelv_VLSI_dev/VLSI_common/models/altera/cyclone/rtl/altera_mf.v:1354. (2) altsyncram 16.57 89 /home/michaelv/tests/michaelv_VLSI_dev/VLSI_common/models/altera/cyclone/rtl/altera_mf.v:42597.
