Occasional ContributorSimulation: override warnings during compilation, and Intel rebranding breaking generated scripts
Hi,
I'm trying to get simulation for IP cores running from the command line.
My first approach was to generate a tcl script using
ip-setup-simulation --output-directory=simulation --quartus-project=test
which gave me a file "mentor/msim_setup.tcl" below the "simulation" directory.
Evaluating this with
vsim -batch <<EOF source mentor/msim_setup.tcl com EOF
failed, as it couldn't find "altera_mf.altera_mf_components" and several others.
Investigating, I stumbled across
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] { ensure_lib ./libraries/altera_ver/ vmap altera_ver ./libraries/altera_ver/
in the generated script -- this seems to set up the libraries for the included components when not using the Altera version of ModelSim that includes precompiled libraries -- but the current version of ModelSim uses "INTEL" in place of "ALTERA", and a hyphen to separate it:
$ vsim -version Model Technology ModelSim - INTEL FPGA STARTER EDITION vsim 2020.1 Simulator 2020.02 Feb 28 2020
Fixing this, I can compile the IP cores in the current project, with lots of warnings like
# ** Warning: (vlog-2070) Existing unprotected design unit "altera_xcvr_reset_control" is being recompiled as protected.
The reason for this is obvious: both the unprotected (in the ..._sim directory) and the protected (in the ..._sim/mentor directory) generated sources are compiled. This seems to have little adverse effect other than doubling compilation time and generating lots of warnings, though.
The top-level components of each IP core seem to be generated inside the "work" library, which is inconsistent with synthesis (where the QIP file uses the instantiation name as a library name), but consistent with the SPD files that don't use a library name, e.g.:
set_global_assignment -library "ddr3_bottom" -name VHDL_FILE [file join $::quartus(qip_path) "ddr3_bottom.vhd"]
in the QIP vs
<file path="ddr3_bottom_sim/ddr3_bottom.vhd" type="VHDL" />
in the SPD.
Adjusting the SPD files and regenerating everything, I can then compile the IP cores that do not have simulation files (like ALTIOBUF) and my actual design, and run the simulation, either interactively
vsim -batch <<EOF set TOP_LEVEL_NAME "tb_serdes" source mentor/msim_setup.tcl elab EOF
or noninteractively
vsim -batch -t ps -L altera_mf_ver -L cyclonev_ver -L cyclonev_hssi_ver tb_serdes <<EOF vcd file tb_serdes.vcd vcd add -r * run -a EOF
All of this still involves manual processes, either because "elab" starts a new instance, so I cannot send a "run -a" as part of the batch, or because I need additional knowledge about which libraries need to be loaded.
My goal is to automate the entire process so I can run it as part of a Continuous Integration pipeline, starting from IP generation (so I don't have to include generated files in version control, and for open source projects, so I don't run into copyright issues).
I have a working pipeline that can synthesize a project with the IP blocks reduced to just their retrieval info by regenerating the IP blocks, and now I'd like to also get simulation to run reliably.
Questions:
- is there a more relevant guide to setting up a scripted simulation environment than chapter 1.9.3 of the User Guide to Megafunctions?
- Are there workarounds or fixes for the problems during generation (names inconsistent with synthesis, warnings generated by double definitions, wrong library path due to failing check for "ALTERA")?
- Is there a good way to extract the names of libraries used, so I can automatically generate an appropriate command line for noninteractive simulation?
Simon
