Forum Discussion
Hi Simon,
To answer your questions:
- We have a quick-start tutorial if that's what you're looking for: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-20093-17-0.pdf?wapkw=quick-start%20quartus%20pro
- I see that you're using the Cyclone V. Because this device is rather old, Quartus will use the older IP that are still under "Altera" for your project. Another reason why you're seeing this issue is that you're using a ModelSim version that is incompatible to your Quartus software. I believe that Quartus will use the older IP because of these reasons. Can you attach your .qar file so I can investigate?
- As far as I know, there isn't a way to do this. Although, I think this is a counter-productive solution, seeing as the errors relating to the libraries you mentioned are pre-compiled libraries.
Nurina
- SimonRichter4 years ago
Occasional Contributor
Hi Nurina,
I've made a quick demo project that shows the problem, with just a PLL and a DDIO as IP components. My simulation setup was really close to the quickstart tutorial already, and I've redone it in the test project to rule out errors here.
The `sim.tcl` script included in the archive follows the layout of the template generated from the quickstart tutorial, the `sim.sh` just wraps generation and ModelSim invocation:
ip-setup-simulation --output-directory=simulation --quartus-project=sim_test cd simulation vsim -batch -do ../sim.tclInconsistent names
The name of the "doubler" component (the PLL in the test project) is doubler.doubler in synthesis, and requires a use clause, but work.doubler during simulation. I can work around that with pragmas, but that is far from ideal:
-- synthesis read_comments_as_HDL on -- library doubler; -- use doubler.doubler; -- synthesis read_comments_as_HDL offto make the library import conditional on synthesis, and
-- synthesis translate_off pll_inst : entity work.doubler -- synthesis translate_on -- synthesis read_comments_as_HDL on -- pll_inst : entity doubler.doubler -- synthesis read_comments_as_HDL offto use the imported name during synthesis, and the name inside `work` during simulation. The DDIO component is not affected, as it uses an older format and is never loaded into a separate namespace (I also need to explicitly compile that in my sim.tcl script, as no SPD file exists for this component, so it is ignored by ip-setup-simulation).
Recompilation of shipped libraries
The generated ModelSim setup script (simulation/mentor/msim_setup.tcl) has a conditional section that isn't supposed to be executed when using the ModelSim included with Quartus, which recompiles the shipped libraries. For the simple project, that isn't much of an issue (just takes longer), but for the project that uses DDR3 memory and transceivers, these are less optimized models, which increases simulation time.
Removing the section between
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {and the corresponding closing bracket from the generated msim_setup.tcl reduces both compilation time (dev_com becomes a no-op) and uses the shipped libraries.
With the sim.sh script in the QAR file, this can be tested by deleting the "simulation" folder (to start with a clean slate) and invoking the script as
rm -r simulation ./sim.sh fThis applies a (crude) fix that deletes the conditional sections.
My interpretation is that the ModelSim version included with Quartus is supposed to skip these sections always, but the branding update from "ALTERA" to "INTEL" broke this test.
Extracting the library names can be skipped when using the "elab" command as defined by the msim_setup.tcl script -- that includes all necessary -L options, and I can work with that, thanks for the pointer to the quickstart that shows how to actually make this usable.
Simon