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sugi's avatar
sugi
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5 years ago

Simulation of PLL generated by Quartus with Modelsim

Hello,

When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz".

The correct clock waveform was confirmed for the PLL input inclk0. How can I get Modelsim to output correctly from c0, locked?

I uses v files for The source code , and I compile "pll.v", "pll_bb.v", "pll_alpll.v", "altera_mf.v" files in addition to the top module and testbench v files in Modelsim.

7 Replies

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi there

    Do you run enough cycles for your simulation? Have you seen any warning/error during Modelsim compilation?

    thanks.

    Eng Wei

    • sugi's avatar
      sugi
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi,

      I run enough cycles for simulation, but the PLL output c0, locked are "1'hz".

      I have not seen any warning/error during Modelsim compilation.

      Do I need to compile other files?

      • EngWei_O_Intel's avatar
        EngWei_O_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        Hi

        Are all signals that you have seen a Z is at the same hierarchy as input inclk0? Are you seeing Z for all the signals at lower hierarchy or they are at Top level of testbench?

        If you can share a sample example that would be good.

        Thanks.

        Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi there


    Since there's no response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    Eng Wei