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sugi's avatar
sugi
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5 years ago

Simulation of PLL generated by Quartus with Modelsim

Hello, When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz". The correct clock waveform was confirmed for the PLL input inclk0. ...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi there

Do you run enough cycles for your simulation? Have you seen any warning/error during Modelsim compilation?

thanks.

Eng Wei

  • sugi's avatar
    sugi
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    I run enough cycles for simulation, but the PLL output c0, locked are "1'hz".

    I have not seen any warning/error during Modelsim compilation.

    Do I need to compile other files?

    • EngWei_O_Intel's avatar
      EngWei_O_Intel
      Icon for Frequent Contributor rankFrequent Contributor
      5 years ago

      Hi

      Are all signals that you have seen a Z is at the same hierarchy as input inclk0? Are you seeing Z for all the signals at lower hierarchy or they are at Top level of testbench?

      If you can share a sample example that would be good.

      Thanks.

      Eng Wei

      • EngWei_O_Intel's avatar
        EngWei_O_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        5 years ago

        In your modelsim script can you try to add below lines:

        add wave /<your_testbench_top>/<your_top_design>/<your_signal_hierarchy_level>/*
        view structure
        view signals
        run -all