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sugi's avatar
sugi
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5 years ago

Simulation of PLL generated by Quartus with Modelsim

Hello, When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz". The correct clock waveform was confirmed for the PLL input inclk0. ...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi there


Since there's no response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Eng Wei