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sugi's avatar
sugi
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4 years ago

Simulation of PLL generated by Quartus with Modelsim

Hello, When I generated the PLL with Quartus Prime Lite and simulated it with Modelsim, the PLL output c0, locked was "1'hz". The correct clock waveform was confirmed for the PLL input inclk0. ...
sugi's avatar
sugi
Icon for New Contributor rankNew Contributor
4 years ago

Hi,

I run enough cycles for simulation, but the PLL output c0, locked are "1'hz".

I have not seen any warning/error during Modelsim compilation.

Do I need to compile other files?

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi

Are all signals that you have seen a Z is at the same hierarchy as input inclk0? Are you seeing Z for all the signals at lower hierarchy or they are at Top level of testbench?

If you can share a sample example that would be good.

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    4 years ago

    In your modelsim script can you try to add below lines:

    add wave /<your_testbench_top>/<your_top_design>/<your_signal_hierarchy_level>/*
    view structure
    view signals
    run -all
    • sugi's avatar
      sugi
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi,

      Thank you for the advice.

      I added a line to the modelsim script, but it didn't change.

      The source code is a simple one created for the PLL test.

      The pll_generate module is set to divide the 50MHz input clock into 25MHz.

      The simulation results are also attached.

      Below source code

      ///////////////////////////////////////////////////

      module test_pll(
      CLK50M,
      RESET
      );

      input CLK50M;
      input RESET;
      wire CLK25M_pll;
      wire locked;

      pll_generate U_pll_generate (
      .areset (RESET ),
      .inclk0 (CLK50M ),
      .c0 (CLK25M_pll ),
      .locked (locked )
      );

      endmodule

      /////////////////////////////////////////////////

      Below simulation result

      • EngWei_O_Intel's avatar
        EngWei_O_Intel
        Icon for Frequent Contributor rankFrequent Contributor
        4 years ago

        Hi there

        Are you able to share your sample proj? Would like to look at your entire setup including the testbench.

        Thanks.

        Eng Wei