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MCost7's avatar
MCost7
Icon for New Contributor rankNew Contributor
7 years ago

Simulation behavior didn't match with synthesized design

The quartus version 18.1 is used, the target FPGA is Stratix IV. The code that is not correctly synthesized is: assign addr = (sel1 & sel2) ? (dst == 3'b001) : (dst == 3'b000); But the simul...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

  • 'I'm not really familiar with Verilog, but it seems to me the second part is only equal to the first part when dst = 3'b000'

Yes, you are correct, first part covers only two combination out of all combination( as in 2nd part).

Please go through the Online training,

https://www.intel.com/content/www/us/en/programmable/support/training/course/ohdl1120.html

  • 'Does your simulion cover all the cases?'

It should be.

  • 'I might have missed deleted comments but I don't see anything about a quartus report that the above posts mentions.'

Quartus report here I mean Quartus synthesis & simulation results.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)