appu69
New Contributor
New ContributorSimulating gate delays
Hey!
I recently started using Intel Quartus Prime Lite edition for simulating Verilog codes.
I came across the topic of gate delays in a book..
for eg. In a verilog code if I write a line of code as such :
module simple_circuit(A, B, C, D, E);
input A, B, C;
output D, E;
and #30 G1 (w1, A, B);
not #10 G2 (E,C);
or #20 G3 (D, w1, E);
endmodule
how do I view the simulation of gate delays.?
