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appu69's avatar
appu69
Icon for New Contributor rankNew Contributor
7 years ago

Simulating gate delays

Hey! I recently started using Intel Quartus Prime Lite edition for simulating Verilog codes. I came across the topic of gate delays in a book.. for eg. In a verilog code if I write a line of code...
AnandRaj_S_Intel's avatar
AnandRaj_S_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Look into example from below link.

https://wiki.eecs.yorku.ca/course_archive/2012-13/F/3201/_media/tutorial_quartusii_timing_simulation_verilog.pdf

If you are using modelsim/VWF

Launch gate level simulation from tools/VWF->Run simulation Tools->Gate level/timing simulation. Before that you need to setup path go to tools->options->EDA Tools option->modelsim altera ->give the modelsim path example "C:\intelFPGA\17.0\modelsim_ase\win32aloem".

You can find more useful information from previous threads kindly check below threads.

https://forums.intel.com/s/question/0D50P00003yyIOXSA2/i-have-problem-with-functional-simulation-with?language=en_US

https://forums.intel.com/s/question/0D50P00003yyGJwSAM/help-whats-the-difference-between-functional-simulation-and-timing-one?language=en_US

Regards

Anand