Simulating Cyclone V Native PHY (15.0)

I am trying to simulate the C-V Native PHY. I'm using what I think is the simplest possible configuration: single transmitter and receiver (no channel bonding), data to transmit are single 8-bit bytes, with 8b/10b coding turned on and byte serializer/deserializer and rx byte ordering off. Receive RX rate match FIFO is also disabled. Transmit bit slip is disabled. For simplicity, I loop the serial transmit data back into the serial receive data input.

The reset core is used to reset the PHY. After a short time, the PHY resets are removed, the receiver locks to both data and the reference clock, and both transmit and receive ready are asserted.

None of the three word aligner modes work at all. I send K28.5 characters (0xBC on tx_paralleldata with tx_datak set) and I see the correct serialized bits on tx_serialdata, which are (in LSb first order) "1100000101" alternating with "0011111010".

With the word aligner set to the synchronous state machine, 10-bit aligner pattern length and 27C as the align pattern, the receive word aligner never syncs. A few clocks after I start sending the K28.5 character, I see the rx_parallel_data go to the value 0xC3 with rx_datak off. After another 10 clocks, I see rx_paralleldata go to 0xE3 and the rx_errdetect flag goes true. The rx_running_disp is also set. Then thereafter the rx_paralleldata toggles between 0xA1 and 0x41, with the running disparity flag toggling off and on, all the while with the error detect flag remaining asserted.

In the manual mode, it seems as if the signal rx_std_wa_patternalign is completely ignored, and the rx_parallel_data and datak are exactly what I see in the synchronous state machine mode.

For the bitslip mode, I wrote a simple state machine to assert the rx_std_bitslip signal as per the user guide. After ten assertions of the signal I see the 0xBC on the parallel data bus with datak = 1, so it looks as if the bitslip is actually working. So I stop my state machine. And then seven clocks after I see the sync character, the receiver goes back to toggling the parallel data output between 0x41 and 0xA1.

In the above when I say "after X clocks," I mean "after X toggles of rx_std_clkout(0)." That is the clock on which the rx_std_wa_patternalign and the rx_std_bitslip signals are asserted.

So in short the word alignment never works. I must be missing something but I cannot figure it out.

Note that I never use the rx_clkslip input. This signal is described as, "When you turn this signal on, the deserializer performs a clock slip operation to achieve word alignment. The clock slip operation alternates between skipping 1 serial bit and pausing the serial clock for 2 cycles to achieve word alignment. As a result, the period of the parallel clock can be extended by 2 unit intervals (UI) during the clock slip operation. This is an optional control input signal." No timing diagram is shown for this signal, nor is there an explanation of why it should be used vs one of the three word align modes described above.

Does anyone have a working example of this sort of configuration?

Thanks.