Simulating Cyclone V Native PHY (15.0)

Yesterday afternoon I submitted a request to the Altera tech support for an example of a simple single (no channel bonding) transceiver which did 8 bit data, 8b/10b coding and word-aligned with K28.5 characters using the receive bit slip. And this morning, I got such an example. If anyone is interested, I can post it here.

That example works, of course! Which leads to: what was different between my code and the tech support's working example? The only difference was that I followed the documentation and asserted the rx_std_bitslip signal for three rx_std_clkout clocks (although there is a timing diagram showing it asserted for only two). The support code showed the signal asserted for ten clocks and synchronous to the test bench main input clock. The support example also showed the bitslip signal asserted for a total of nine times. He never checks rx_parallel_data and rx_datak to see if the receiver has aligned to the K28.5 character, but after nine bitslips, it aligns.

I changed my test bench to assert the bitslip signal to be ten clocks wide and voila -- it worked.

The obvious question is, then, "why does the bitslip signal need to be asserted for 10 parallel clocks and not the two or three referenced in the documentation?" I've asked for clarification and will post it here, too.

I hope this helps somebody!