Altera_Forum
Honored Contributor
Honored ContributorSimulate UART core in Quartus II
Hello. I design a UART core in VHDL but I can't simulate it in the Quartus II. I follow correctly the ASMD chart of the UART core but the exit never is altered after the simulation. I need your help to simulate it correctly. It follows the diagram of blocks of the UART
http://images.orkut.com/orkut/photos/OgAAABGkWazJBmPyUzzh9njBJ5RQakxvATGFPO6LgwwaRaouRAkypgAOSZaDlj8Q-QxLMLFJHDuMAYaYUt4zSv2HX_wAm1T1UIpwBogt3jKuPISNym7RA1SBzKA3.jpg sorry by my english... thank you so much!
