Simple explaination I hope

  SIGNAL slv         : STD_LOGIC;
  SIGNAL usg_counter : UNSIGNED(7 DOWNTO 0);
  --code to make usg_counter count up 1 count etc. every 1uS here
  
  proc_ConfusedDotCom : PROCESS(usg_counter)
  BEGIN
    slv <= '0';
        
    IF usg_counter = b"0010_0110" THEN
      slv <= '1';
    END IF;
  END PROCESS proc_ConfusedDotCom;

IF usg_counter = b"0010_0110" THEN
      slv <= '1';
else
     slv <= '0';
END IF;

Cool!

The default approach is convenient alternative if the target signal is to be assigned same value in many following statements in the sequence.

The most common usage is in state machines where output signals are usually the default, but assigned something different in specific states.

Gotcha.

  proc_Counters : PROCESS(IN_CLK, IN_RESETn)
  BEGIN
    IF IN_RESETn = '0' THEN
      usg_Counter <= (OTHERS => '0');
      slv <= '0';
        
    ELSIF RISING_EDGE(IN_CLK) THEN
      IF usg_Counter = b"0010_1111" THEN
        usg_Counter <= (OTHERS => '0');
      ELSE
        usg_Counter <= usg_Counter + 1;
      END IF;
        
      --Put it here instead...
      IF usg_Counter = b"0010_0110" THEN
        slv <= '1';
      ELSE
        slv <= '0';
      END IF;
        
    END IF;
  END PROCESS proc_Counters;

yes, but it has a 1 clock cycle delay compared to the unregistered code.

REALLY!

the get the same behaviour, you need to make the counter a variable, check the variable rather than the signal.

the combined one has the extra clock cycle delay, as you make slv synchronous. The seperated one has no interaction with the clock.

I see!