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I have seen some VHDL code written like this:
SIGNAL slv : STD_LOGIC;
SIGNAL usg_counter : UNSIGNED(7 DOWNTO 0);
--code to make usg_counter count up 1 count etc. every 1uS here
proc_ConfusedDotCom : PROCESS(usg_counter)
BEGIN
slv <= '0';
IF usg_counter = b"0010_0110" THEN
slv <= '1';
END IF;
END PROCESS proc_ConfusedDotCom;
Can some clever bod explain exactly what is happening to the signal 'slv' here please? Is there a better way of writing this?
I know what is does, I would like to know why. :)
Cheers,
Andy
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it is equivalent to
IF usg_counter = b"0010_0110" THEN
slv <= '1';
else
slv <= '0';
END IF;
or just:
slv <= '1' when usg_counter = b"0010_0110" else '0';
In your code the '0' is assigned as default and the next conditional statement updates it.
Honored Contributor
