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Altera_Forum's avatar
Altera_Forum
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11 years ago

Simple explaination I hope

I have seen some VHDL code written like this: 


  SIGNAL slv         : STD_LOGIC;
  SIGNAL usg_counter : UNSIGNED(7 DOWNTO 0);
  --code to make usg_counter count up 1 count etc. every 1uS here
  
  proc_ConfusedDotCom : PROCESS(usg_counter)
  BEGIN
    slv <= '0';
        
    IF usg_counter = b"0010_0110" THEN
      slv <= '1';
    END IF;
  END PROCESS proc_ConfusedDotCom;

Can some clever bod explain exactly what is happening to the signal 'slv' here please? Is there a better way of writing this?

I know what is does, I would like to know why. :)

Cheers,

Andy

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    no, this is to do with the way signals vs. variables work.

    signals are updated only when the process they are assigned in suspends. So a signal assignment actually schedules the update to occur in the next delta cycle, or in x ns if you use the after assignments:

    x <= '1' after 10 ns;

    varaibles are updated immediatly, hence why making the counter a variable instead of a signal would remove a clock delay from the process. It wouldnt exactly recreate the same hardware, as the two versions would alter the position of the output register - with separate processes the register is on the counter with the slv signal just a gated version of this register output. In the combined version, the slv is a gated version of the +1 output, with the register placed after this.

    Hence why you really need to understand the underlying hardware before writing the VHDL.