Honored Contributor
Honored Contributorno, this is to do with the way signals vs. variables work.
signals are updated only when the process they are assigned in suspends. So a signal assignment actually schedules the update to occur in the next delta cycle, or in x ns if you use the after assignments: x <= '1' after 10 ns; varaibles are updated immediatly, hence why making the counter a variable instead of a signal would remove a clock delay from the process. It wouldnt exactly recreate the same hardware, as the two versions would alter the position of the output register - with separate processes the register is on the counter with the slv signal just a gated version of this register output. In the combined version, the slv is a gated version of the +1 output, with the register placed after this. Hence why you really need to understand the underlying hardware before writing the VHDL.
