signed integer to std_logic_vector and vise versa

Question

Hello Altera people !

I have two questions :

1 // I need to read a signed integer and compare it in vhdl !

Knowing that the output is std_logic (either vector or simple). how to do it ? what are the instructions !?

2// The component will be used as user peripheral in Qsys so I guess the input isn't considered as integer no ? the input is 32 bits how I can do my comparison as if it is signed integer ?!

thnx

altera_forum · Answer

use ieee.numeric_std.all;  signal slv : std_logic_vector(10 downto 0); signal uns : signed(10 downto 0);  uns &lt;= SIGNED(slv);

altera_forum · Answer

--- Quote Start ---

use ieee.numeric_std.all;

signal slv : std_logic_vector(10 downto 0);

signal uns : signed(10 downto 0);

uns <= SIGNED(slv);

--- Quote End ---

This is my favorite graphic on VHDL conversions: http://www.bitweenie.com/listings/vhdl-type-conversion/

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signed integer to std_logic_vector and vise versa

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