Forum Discussion

Honored Contributor

9 years ago

signed integer to std_logic_vector and vise versa

Hello Altera people ! I have two questions : 1 // I need to read a signed integer and compare it in vhdl ! Knowing that the output is std_logic (either vector or simple). how to do it ? wh...

Altera_Forum

Honored Contributor

9 years ago

--- Quote Start ---

use ieee.numeric_std.all;

signal slv : std_logic_vector(10 downto 0);

signal uns : signed(10 downto 0);

uns <= SIGNED(slv);

--- Quote End ---

This is my favorite graphic on VHDL conversions: http://www.bitweenie.com/listings/vhdl-type-conversion/

Forum Discussion

signed integer to std_logic_vector and vise versa

Recent Discussions

ram retiming

Reset Release IP for Agilex needs Stratix 10 device files installed!

Licensing ‘Know-How’ Guide

Timing analysis - long combinational path

Invalid license key (inconsistent authentication code)