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Altera_Forum
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9 years ago

signed integer to std_logic_vector and vise versa

Hello Altera people ! I have two questions : 1 // I need to read a signed integer and compare it in vhdl ! Knowing that the output is std_logic (either vector or simple). how to do it ? wh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

use ieee.numeric_std.all;

signal slv : std_logic_vector(10 downto 0);

signal uns : signed(10 downto 0);

uns <= SIGNED(slv);