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Altera_Forum's avatar
Altera_Forum
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11 years ago

signed and unsigned no effect?

Hi,

Im using modelsim on something of what would be a lowpass filter code in my DSP experience.

But modelsim does not produce a different output on this "signed" variable. Can I get this behavour from verilog?

module module

(

input clock,

input [23:0] in,

output reg signed[23:0] out = 0

);

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    You dont show what you're actually doing. But varaibles are treated as unsigned unless you explicitly declare them signed. And then verilog behaviour means if you add two unsigned values you get an usigned result.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Had a fresh look at it, and it worked right away today.

    All the used variables had to be labeled as signed. Opposed to just the output register.