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Altera_Forum's avatar
Altera_Forum
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17 years ago

SignalTap and (re-)compile time

I'm using SignalTap on a very large design which takes ~5hr to incrementally compile on some of the fastest machines available (3GHz dual cores with 32G memory, 12MB cache and 1300MHz FSB).

I recall when Altera first introduced SignalTap that the claim was that we'd be able to use it like Xilinx - i.e. introduce Signal Taps post compilation effectively using a netlist editor.

Does anyone know if that ever made it ? Or is it true that whenever you want to introduce a new tap (or move an old one) you have to go round an incremental synthesis / place and route process rather than simply route the one new signal to the right place in the floorplan and check it can meet timing ?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    If you are modifying connections to the SignalTap internal embedded logic analyzer, then you have to go through whatever flow is currently documented in the device handbook. It has been changing over the last several Quartus versions, but it is now tightly integrated with the incremental compilation feature.

    If you are using QII 8.1 and correctly setting the entire design other than the embedded logic analyzer to post-fit when making small SignalTap changes, then I'm surprised the recompile takes 5 hours. In the past some things like physical synthesis could make a recompile with incremental compilation take longer than you would expect, but I thought that was improved by version 8.1.

    If you want to route a signal to a pin:

    Altera has what they call an ECO (engineering change order) flow that uses the Chip Planner. The user can add a connection without rerunning the entire Fitter step.

    The SignalProbe feature has long been available for routing debug signals out to pins without a full recompile. A few Quartus versions back this flow changed to be an essentially automated way to use the ECO flow.

    There are other debug features documented in the volume of the Quartus handbook that covers SignalTap. One of them lets you route signals out to an external logic analyzer. To see multiple signals on a few debug pins, you can dynamically select a subset of signals from the larger set of signals that were designated before compilation.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Signalprobe rather than Signaltap - that's exactly the answer I was looking for.

    Assuming I can get it going, I'll post how long the ECO compile takes later.

    Many thanks.