Honored Contributor
Honored ContributorIf you are modifying connections to the SignalTap internal embedded logic analyzer, then you have to go through whatever flow is currently documented in the device handbook. It has been changing over the last several Quartus versions, but it is now tightly integrated with the incremental compilation feature.
If you are using QII 8.1 and correctly setting the entire design other than the embedded logic analyzer to post-fit when making small SignalTap changes, then I'm surprised the recompile takes 5 hours. In the past some things like physical synthesis could make a recompile with incremental compilation take longer than you would expect, but I thought that was improved by version 8.1. If you want to route a signal to a pin: Altera has what they call an ECO (engineering change order) flow that uses the Chip Planner. The user can add a connection without rerunning the entire Fitter step. The SignalProbe feature has long been available for routing debug signals out to pins without a full recompile. A few Quartus versions back this flow changed to be an essentially automated way to use the ECO flow. There are other debug features documented in the volume of the Quartus handbook that covers SignalTap. One of them lets you route signals out to an external logic analyzer. To see multiple signals on a few debug pins, you can dynamically select a subset of signals from the larger set of signals that were designated before compilation.
