Signal tap doesnt recognise most of the entities of my bdf file. Compilation doesn't fit too

The likely reason for the reduced resource usage is that some elements were found to contribute nothing to the functionality of the circuit during synthesis and were optimized away.

Check the Compilation Report, Optimization, Nodes Swept Away During Synthesis to ensure there are no major part of your design missing. While it's normal for synthesis to eliminate some registers, a significant reduction in resources usually indicates a design issue.

You mentioned that resource usage dropped after modifying Pulse_Minimum_V4_ind_RESET. I recommend reviewing that modification to check for potential errors.

If you need further debugging assistance, please share your .qar file (Project > Archive Project).

Additionally, I recommend running the design in VHDL instead of BDF, especially as designs become more complex.

Regards,

Richard Tan