Signal tap doesnt recognise most of the entities of my bdf file. Compilation doesn't fit too

Without seeing the design itself, it's hard to figure this out, but most likely, the logic is getting optimized away because it is not connected to anything, like an I/O pin. If you want to prevent logic from being optimized away, connect its outputs to an actual I/O pin or use virtual pin assignments to create logic "stubs" that will prevent this.

Check the compilation report in more detail. If logic is optimized away, it's usually mentioned in there somewhere.