New ContributorSignal tap doesnt recognise most of the entities of my bdf file. Compilation doesn't fit too
Good morning colleagues,
I need your help with a problem I have encountered with Quartus Prime Lite Software while programing my MAX10 FPGA 10M08SCE144I7G. I have made a design in Quartus to manage some semiconductor triggers. I have made designs in vhd that I have converted to blocks and after that, I have put them in bigger blocks. I have been working on this design and when compiling, synthesising, etc... it took about 1 minute and the design occupied 1400 logical units. However, I have made a modification of the design ‘Pulse_Minimum_V4_ind_RESET’ and when I put it in my block diagram and compile I see that it does it successfully but it takes only about 30 seconds and occupies only 500 logical units. When I open signal tap to debug the design, I see that the block ‘BLOQ_MIN_DEAD’ shows me only the instance ‘Generador_Disparos_v1_ind’ inst4 but however the instance of the same block inst5 does not show me and also does not show me the instances of ‘Pulso_Minimo_C4_ind_RESET’ that I have implemented. Honestly, I dont know what is happening because I have never had this kind of problem. I think that it is not only related to signal tap but also with the compilation because now it takes much less logic elements than before.
I attach you some captures of the design and if you could let me know what could be happening would be a great advance in my development. Thank you in advance
BR,
Pedro
