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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signal probe pins flow?!

Dear Altera-Form community,

I would like to measure an internal FPGA (Stratix IV) signal with an oscilloscope. Therefore I tried to use Quartus' 11.1 Signal Probe tool. I clicked on "Tools->Signal Probe Pins..." in the menu bar and selected the signal I wanted to see. I assigned a valid, unused pin and then hit the "Start Check & Save Netlist changes" which starts a new signal probe compilation. Everything worked fine, no error appeared in the messages view. The changes were even shown in the change manager.

Then I programmed the FPGA. However, i couldn't see the signal's value (and I know this signal exists) on the pin.

On further investigation I discovered that the .sof-file's date was the time I did the last full compilation, which is totally different to the time I compiled the ECOs with the Signal Probe tool...

So could you please tell me what I did wrong?!

Thanks for any replays... :)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi!

    I figured out, what was wrong...

    During compillation of the ECOs, the quartus showed the warning "Can't generate netlist output files because the encrypted file "xxxx" is not the same file for Analysis & Synthesis."

    Sorry, I forgot what the name of the file was. However, it was generated by the Signal Tap II-Tool....

    After removing all Signal Tap instances, the Signal Probe feature worked well!