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Altera_Forum
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13 years ago

Signal probe pins flow?!

Dear Altera-Form community, I would like to measure an internal FPGA (Stratix IV) signal with an oscilloscope. Therefore I tried to use Quartus' 11.1 Signal Probe tool. I clicked on "Tools->Sig...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi!

I figured out, what was wrong...

During compillation of the ECOs, the quartus showed the warning "Can't generate netlist output files because the encrypted file "xxxx" is not the same file for Analysis & Synthesis."

Sorry, I forgot what the name of the file was. However, it was generated by the Signal Tap II-Tool....

After removing all Signal Tap instances, the Signal Probe feature worked well!