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Altera_Forum's avatar
Altera_Forum
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12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi ,

I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code).

I am successful in simulating the code but while I tried to implement in the design it gave me following error:

"Signal output cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."

I am not sure what is this error about. Below is my part of code which I guess is giving this error:

process(clk_plstr,plsrep) ----clk_plstr=10mhz;plsrep=2.5khz

begin

pls<=conv_std_logic_vector(n,12);

if rising_edge(clk_plstr)then

count<= count+'1';

end if;

if(count<=pls)then

if(clk_plstr'event and clk_plstr = '1')then

output<='0';

else

output<='1';

end if;

else

output<='0';

end if;

if (plsrep='1')then

count<=B"000000000000";

end if;

end process;

fout<=output;

It would be very helpful if anyone can point out the problem by which I am getting this error.

I would really appreciate your help.

Thank you

14 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    This is the whole code which I am working right now:

    process(clk_plstr,plsrep)

    begin

    if(plsrep='1')then

    count_reg<=B"000";

    end if;

    if(clk_plstr'event and clk_plstr='1') then

    count_reg<=count_next;

    if(count_reg<=pls )then

    output<='1';

    else

    output<='0';

    end if;

    end if;

    end process;

    count_next <=count_reg+'1' when(count_reg=B"000" and plsrep='1') else

    count_reg when (count_reg=B"000") else

    count_reg+'1' when (count_reg<pls)else

    --count_reg;

    B"000";

    fout<=output;

    end Behavioral_plstr;

    It might be I have done some silly mistake.

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Well, you should have clk_plstr as an elsif to the plsrep. With the current code the plsrep is NOT a reset, as the clk gets priority over the reset. You should also assign output in the async reset part, or it will use the plsrep as a synchronous enable.

    And this still doesnt show the source of clk_plstr like I asked.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Missing elsif makes the "bad synchronous description".

    Clock source is interesting related to timing analysis but doen't affect the synthesis of the shown code.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    I had made some small mistake and I figured it out.

    Thank you bertulus and tricky for explanation.