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Altera_Forum's avatar
Altera_Forum
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12 years ago

Signal output cannot be synthesized, bad synchronous description.

Hi , I have been using vhdl programming for my project and I am trying to make a counter to count clock signal(clk_plstr),the counter is reset with another pulse signal(plsrep in my code). I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Well, you should have clk_plstr as an elsif to the plsrep. With the current code the plsrep is NOT a reset, as the clk gets priority over the reset. You should also assign output in the async reset part, or it will use the plsrep as a synchronous enable.

And this still doesnt show the source of clk_plstr like I asked.