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PhilipJ451's avatar
PhilipJ451
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6 years ago

signal from input pin to output pin inverted

I am designing with Quartus Prime v19.1.0 for a Cyclone 10 device. I have two clock inputs into the design and for convenience I feed these signals to output pins with test points connected (along ...
PhilipJ451's avatar
PhilipJ451
Icon for New Contributor rankNew Contributor
6 years ago

Sorry All, ignore this!!

Confusion with another part of the system (not FPGA) generating the signal the wrong way up, and me getting confused on the oscilloscope between 1/2 the period of the clock (~20nS) and the natural delay through the FPGA from input pin to output pin

regards

PhilipJ