Show delays of path in chip planner

Hi,

In the Chip Planner, I use "Generate Fan-In/Out Connections" to figure out the connection between two related nodes (lut, or register). But I can't see the delay between them, for example, from one lut to another lut. The "Show Dealys" button doesn't make any difference.

The quartus edition that I use are 11.0, 13.1, 15.1. And the FPGA is EP4CE115F29I7N. Is there something that I missed? Or, are there any other ways to help me get the delay?

Thank you!