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Altera_Forum's avatar
Altera_Forum
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12 years ago

seven segment display

hey everyone,

I am trying to write a code in Verilog which should display from 00 to FF on seven segment. i have two segment display on my fpga board.

It will be great if somebody can help me with code snippet. For convenience i am posting my code.

Do let me know where I am making the mistake. Hope to hear soon.

This is the code:

module hex2count(clk, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);

input clk;

output[6:0] HEX0;

output[6:0] HEX1;

output[6:0] HEX2;

output[6:0] HEX3;

output[6:0] HEX4;

output[6:0] HEX5;

output[6:0] HEX6;

output[6:0] HEX7;

//counter register

reg [39:0] counter ;

reg [3:0] shortCount ;

reg [6:0] HEX0, HEX1 ;

always @ (counter)

begin

case (counter[28:25])

4'h0: HEX0 = 7'b1000000;

4'h1: HEX0 = 7'b1111001;

4'h2: HEX0 = 7'b0100100;

4'h3: HEX0 = 7'b0110000;

4'h4: HEX0 = 7'b0011001;

4'h5: HEX0 = 7'b0010010;

4'h6: HEX0 = 7'b0000010;

4'h7: HEX0 = 7'b1111000;

4'h8: HEX0 = 7'b0000000;

4'h9: HEX0 = 7'b0010000;

4'ha: HEX0 = 7'b0001000;

4'hb: HEX0 = 7'b0000011;

4'hc: HEX0 = 7'b1000110;

4'hd: HEX0 = 7'b0100001;

4'he: HEX0 = 7'b0000110;

4'hf: HEX0 = 7'b0001110;

default HEX0 = 7'b1111111;

endcase

case (counter[32:29])

4'h0: HEX1 = 7'b1000000;

4'h1: HEX1 = 7'b1111001;

4'h2: HEX1 = 7'b0100100;

4'h3: HEX1 = 7'b0110000;

4'h4: HEX1 = 7'b0011001;

4'h5: HEX1 = 7'b0010010;

4'h6: HEX1 = 7'b0000010;

4'h7: HEX1 = 7'b1111000;

4'h8: HEX1 = 7'b0000000;

4'h9: HEX1 = 7'b0010000;

4'ha: HEX1 = 7'b0001000;

4'hb: HEX1 = 7'b0000011;

4'hc: HEX1 = 7'b1000110;

4'hd: HEX1 = 7'b0100001;

4'he: HEX1 = 7'b0000110;

4'hf: HEX1 = 7'b0001110;

default HEX1 = 7'b1111111;

endcase

end

endmodule

Regards

Muzammil

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi, what you get on your 7seg display ?

    I suppose the counter is counting :-).

    clk is clocking :-)

    Did you assign pins correctly ? Yes I suppose.

    I don't know Verilog : you have output[6:0] hex0; output[6:0] hex1; and later reg [6:0] hex0, hex1 ;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    Hi, what you get on your 7seg display ?

    I suppose the counter is counting :-).

    clk is clocking :-)

    Did you assign pins correctly ? Yes I suppose.

    I don't know Verilog : you have output[6:0] hex0; output[6:0] hex1; and later reg [6:0] hex0, hex1 ;

    --- Quote End ---

    Its just getting disappeared. I mean to say when code is downloaded seven segment flashes for a moment and goes off.

    This is the problem I am facing now.

    Don't know what to do now.

    Regards

    Muzammil
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Did you simulate it? If no, do.

    Is this one file? Or do you have a higher level? Check your warnings for inferred wires. That warning means your bus wasn't defined as being N wide, and was reduced to 1 wide.