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Altera_Forum's avatar
Altera_Forum
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12 years ago

seven segment display

hey everyone, I am trying to write a code in Verilog which should display from 00 to FF on seven segment. i have two segment display on my fpga board. It will be great if somebody can help m...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Did you simulate it? If no, do.

Is this one file? Or do you have a higher level? Check your warnings for inferred wires. That warning means your bus wasn't defined as being N wide, and was reduced to 1 wide.