set_output_delay specification for defined edge delay

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i have an output bus, which has to provide new data 15..20ns after the rising edge of the input clock. clock period is 61ns.

with the classic timing analyzer, i had TCO defined as 20ns and MTCO as 15ns.

how do i have to define this using set_output_delay?

defining this requirement as Tsu and Th results in:

Tsu = 61ns - 20ns = 41ns

Th = 15ns

but i do not understand how to define this using the set_output_delay construct.

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with classic analyser, for your case I will set minimum Tco to 15 and maximum Tco to period-20.

With Timequest, my current understanding from altera documents is this:

maximum delay = setup of dest. register (i.e. 20 ns if we assume equal clk/data delay). and minimum delay is -hold time (-15ns again if we assume equal data/clk delay).

However that applies to clk going out with data. In your case you refer to input clk and thus you should adjust the figures as clk/data delay now is double even on equal trace.

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Is the set_output_delay a part of the Altera standard library and if so how do I initialize it?

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Hi lew3611,

Bongo is right, it is an command for the TimeQuest Timing Analyzer. It defines the output timing requirements ( that depends on the input requirements of the receiving device). It does not mean that you switch on/off delays.

Kind regards

GPK

Oh ok, well I have no experience with the TimeQuest Analyzer. Thanks for the info. I figured the only way that I was going to learn this software was to just jump in on other convos so that I could get an indirect lesson on how to actually use it!

Lew