Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

set_output_delay specification for defined edge delay

i have an output bus, which has to provide new data 15..20ns after the rising edge of the input clock. clock period is 61ns. with the classic timing analyzer, i had TCO defined as 20ns and MTCO...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Oh ok, well I have no experience with the TimeQuest Analyzer. Thanks for the info. I figured the only way that I was going to learn this software was to just jump in on other convos so that I could get an indirect lesson on how to actually use it!

Lew