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Altera_Forum
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15 years ago

set_output_delay specification for defined edge delay

i have an output bus, which has to provide new data 15..20ns after the rising edge of the input clock. clock period is 61ns. with the classic timing analyzer, i had TCO defined as 20ns and MTCO...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Is the set_output_delay a part of the Altera standard library and if so how do I initialize it?

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Hi lew3611,

Bongo is right, it is an command for the TimeQuest Timing Analyzer. It defines the output timing requirements ( that depends on the input requirements of the receiving device). It does not mean that you switch on/off delays.

Kind regards

GPK