Forum Discussion

JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
7 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift.

The design is working but we have detected that "set_output_delay" dosen't apply. For example, we have compared, in an oscilloscope, the delay beetwen the signals CLK and a bit ADD[15] bus and it is constant for any "set_out_delay".

We are using the next constrains configuration:

create_clock -name RAM_CLK -period 16 [get_ports {RAM_CLK}]

create_generated_clock -name vt_RAM_CLK -source [get_ports {RAM_CLK}] -divide_by 1 -multiply_by 1 -phase 180

set_output_delay -clock {vt_RAM_CLK} 3 [get_ports {RAM_ADD[15] }].

In next figure, you can see timing of both signals.

The delay is contant for any "output_delay" value (0, 1, 2, 3..).

23 Replies

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    What is the max and min output delay? Is it within range?

    Can you report Ignored Constraints and see if the set_output_delay constraint is being ignored?

    Thanks.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks for your email.

    The constraints are not included in ignored constraints report.

    We tried with delay between 0 to 8. With the same and different max / min values.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi,

    The phisical delay beetwen both signals is always the same, about 0ns

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    May I know the software version and edition? Can you share the test case for investigation?

    Thanks

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    I check the project.qar, the output delay is the same as the value in the .sdc file

    Example 1:

    Example 2:

    Thanks.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    7 years ago

    Thanks for your email.

    I know that the delay in the Timequest simulation is correct, probably I forgot to comment it. The problema is I dont see this delay monitoring the signal in the oscilloscope.

    Regards.

  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi,

    The delay is always the same.

    Can you test the output signals in a test board o similar?

    Regards