Forum Discussion

JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
7 years ago

Set_output_delay commands does not apply to the output signal

We have a design where we control an external RAM memory. We generate the CLK and control memory signals in a FPGA (Cyclone IV). The CLK signal is generated using a PLL, with 180º phase shift. The ...
JOter's avatar
JOter
Icon for New Contributor rankNew Contributor
7 years ago

Thanks for your email.

I know that the delay in the Timequest simulation is correct, probably I forgot to comment it. The problema is I dont see this delay monitoring the signal in the oscilloscope.

Regards.