set_max_delay and set_min_delay is no sense for project compile

Hi sir,

I face one problem, and I have no idea for the set_max_delay and set_min_delay constrains, the problem as follows:

I want to constrains the delay from the reg_q to the port_o, but I found there is no effect when I constrain the datapath, and the time report presents the delay is large the value that I set.

The timing report as follows:

the constrains as follows:

set_min_delay -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 0.200

set_max_delay -from spi_master_wrap_u|spi_tx_u|tx_sck_o|q -through spi_master_wrap_u|sck_o~0|combout -to m_spi_ck_o~output|i 2.100

Is there any problem for the constarins or it's not correct to use these constrains. Would someone will help me?

Software:quartus II 13.1

FPGA chip: Arria V AGXA7

Best regards,

Lambert