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lambert_yu's avatar
lambert_yu
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5 years ago

set_max_delay and set_min_delay is no sense for project compile

Hi sir, I face one problem, and I have no idea for the set_max_delay and set_min_delay constrains, the problem as follows: I want to constrains the delay from the reg_q to the port_o, b...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


It depends on the location of the source and destination. If you set min/max delay and you see the delay in the Timing Analyzer exceeds the value that you set, the value in the Timing Analyzer is min/max for the same source/destination location.


Thanks

Best regards,

KhaiY


  • lambert_yu's avatar
    lambert_yu
    Icon for Contributor rankContributor
    5 years ago

    Hi KhaiY,

    If so, I want to know, if the max/min value which I set is not satisfied by software, will it provide violation message? Now, it does not present this message in timing report, it's normal?

    BR,

    Lambert