Occasional ContributorHello,
The user guide for the Serial Lite III IP defines a ready_tx signal as follows:
Question:
Under what circumstances can the adaptation FIFO reach partial full?
Doesn't the IP support full data rate (when valid_tx is asserted contiguously) ?
Frequent ContributorHi,
In normal operation, on the Source Core, the interface clock is faster than the user clock, hence the adaptation FIFO should never reach partially full.
The adaptation FIFO will only reach partially full or even overflow, when the link status becomes abnormal. That’s when you need to backpressure the valid_tx.
Sorry, I don’t get the full data rate. The SLIII IP support “Basic” (continuous) mode and “FULL” (burst) mode.
Thank you,
Kshitij Goel
Frequent ContributorHi,
As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you,
Kshitij Goel
