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SteveMellor's avatar
SteveMellor
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1 year ago
Solved

Select the PLL reference clock used for timing analysis

When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is th...
Timing
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
1 year ago

I'm not sure why the source clock used matters here, but you could manually add create_generated_clock commands to your .sdc to define the correct source clock for the clock in question if derive_pll_clocks is using the wrong source.