Forum Discussion
SteveMellor
New Contributor
New ContributorSelect the PLL reference clock used for timing analysis
When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is th...
Here is the user guide in case you cannot follow: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/derive-pll-clocks-derive-pll-clocks.html
sstrell
Super Contributor
Super ContributorI'm not sure why the source clock used matters here, but you could manually add create_generated_clock commands to your .sdc to define the correct source clock for the clock in question if derive_pll_clocks is using the wrong source.
