Forum Discussion
SteveMellor
New Contributor
New ContributorSelect the PLL reference clock used for timing analysis
When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is th...
Here is the user guide in case you cannot follow: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/derive-pll-clocks-derive-pll-clocks.html
SteveMellorNew Contributor
New ContributorI have been using derive_pll_clocks but it uses the slower of the two input clocks for timing analysis. The clock tree analysis shows this. Reporting the timing of any path clocked by the output of the PLL also shows that it is using the slower clock period. The device is an Arria 10.
