Forum Discussion
SteveMellor
New Contributor
New ContributorSelect the PLL reference clock used for timing analysis
When a PLL has multiple reference clock inputs how can you define the one to use for timing analysis? The tool is selecting the first reference clock (pll_refclk0) for timing analysis but this is th...
Here is the user guide in case you cannot follow: https://www.intel.com/content/www/us/en/docs/programmable/683068/18-1/derive-pll-clocks-derive-pll-clocks.html
KennyT_altera
Super Contributor
Super ContributorYou may also check your timing report, some of the device like Agilex 7, the derive_pll_clocks is auto inserted. Do let me know if you have further question?
